The subject matter of the present invention relates to input and output buffer circuits. More particularly, the present invention relates to such buffer circuits having a special utility in the interfacing of CMOS circuitry with associated ECL devices.
An ideal digital logic device would have the characteristics of an infinite input impedance as well as a zero output impedance. Moreover, this ideal digital logic device would have a zero propagation delay and power dissipation. With existing technologies, ECL and MOS most nearly approximate the desired infinite input impedance. Additionally, both technologies are fast and about equally satisfy the requirement of zero propagation delay. However, only ECL technologies can approach the zero output impedance requirement while only CMOS comes close to the requirement of zero power dissipation. Resultantly, the combination of ECL and CMOS technologies produce as nearly a perfect logic technology as is available today.
Therefore, ECL MOS technologies have substantial advantages over either technology alone when dealing with nanosecond edge rates and propagation delays. Both ECL and MOS technologies manufacture logic that is capable of this performance between on-chip gates. In addition, ECL is adapted to driving low impedance lines off-chip in a system environment, but does so at the expense of power dissipation. MOS technology has a large advantage with low power consumption but has substantial difficulties in the off-chip, low impedance line environment.
More particularly, low voltage silicon gate CMOS technology is noted for its speed, packing density, and low power dissipation. Disadvantages with CMOS technology lie in its inability to drive lines in a high speed system environment where 50 to 100 ohm line drivers are necessary. In general however, ECL does not pack as well as CMOS and dissipates considerably more power. ECL also has an advantage in the existence of a very large family of fast "glue" MSI to couple large systems together.
There have previously been reported devices attempting to merge ECL and CMOS technologies to take advantage of the inherently desirable aspects of each. See for example Yu et al "C-MOS Static RAM Feels at Home With ECL Speeds" Electronics, Feb. 10, 1982 at pp. 160-163. In this regard, ECL input and output buffers have been provided for a CMOS circuit device. However, the input buffer to such circuitry has been relatively complex and power hungry in its adaptation of a conventional -0.7 to -1.9 ECL logic level to a conventional 0 to -5.2 volts CMOS logic level. Propagation delays of up to 4.5 nanoseconds have been reported in the amplification and level shift between the ECL and CMOS logic levels. Moreover, the propagation delays and power comsumption reported have been due primarily to the disparate nature of these two logic levels since the CMOS circuitry is operated at a full five volt logic swing. Moreover, the conventional five volt CMOS logic swing causes known problems when dealing with fine line device geometries of one micron or less. These disadvantages include an increased susceptibility to punchthrough and undesirable short channel effects.
Although in utilizing the conventional five volt logic swing for the CMOS devices, the ECL output buffer circuit is considerably simplified, the overriding benefits to be derived from using a lesser CMOS logic swing by simplification of the associated ECL input buffer greatly outweigh the necessity of a somewhat more complex ECL output buffer with the lower voltage CMOS logic swing.
It would therefore be highly desirable to provide improved ECL MOS buffer circuits.
It would further be highly desirable to provide improved ECL CMOS buffer circuits which can adapt an ECL logic swing to a lower voltage CMOS logic swing.
It would still further be highly desirable to provide improved ECL MOS buffer circuits which minimize propagation delay and power dissipation.